On May 19, 2015, BENEFIC presented a technical session regarding Energy efficient MPSoC at CATRENE DTC in Dresden, Germany. The session was moderated by Armand Castillejo of STMicroelectronics. The following presentations were given by CEA Leti, IMEC, and TU Delft:
Title: Efficient Power Management in FD-SOI MPSoC (Diego Puschini, CEA)
UTBB FD-SOI technology offers new opportunities and challenges for circuit designers, promising extraordinary power saving and performance figures. This talk reviewed some basic concepts of dynamic power management and how the Dynamic Voltage-Frequency Scaling (DVFS) notion has evolved to Adaptive Voltage-Frequency Scaling (AVFS). With a special focus the constraints imposed by Multi-Processor System-on-Chip (MPSoC) architectures, AVFS is studied taking advantage of FD-SOI opportunities. This talk has presented some results obtained during the Catrene Benefic project: a power management technique that takes advantage of the very wide Body Biasing range offered by UTBB FD-SOI, in combination with efficient Adaptive Voltage and Frequency Scaling techniques. The proposed approach makes use of intelligent power mode selection in order to efficiently increase the total power saving. Results have been estimated on a 32-bit VLIW DSP with a Body Biasing Voltage scaling from 0V up to +/-1.5V combined with an AVFS mechanism in UTBB FD-SOI 28nm.
Title: A single-PCB miniature, efficient, 900MHz Rectenna for RF harvesting (Prof.dr. G. Dolmans, IMEC)
In the last decade, interest in wireless power transfer (WPT) has been reignited and since the latter half of this decade two distinct flavors of WPT have become apparent: short distance WPT by inductive charging and long distance WPT by RF transmission and reception. The main reason for renewed interest in longer distance, is believed due to the success of RFID and the recent advances in realizing low power electronics. With wireless sensors demanding average DC power in the range of tens of microwatts instead of tens of milliwatts, it has become feasible to power these sensors with long distance WPT. The recent advances of Holst Centre / Imec for a miniature 900 MHz long distance WPT system is shown, with improvements in sub-systems such as antenna, impedance matching circuits, rectifier circuits, boost-buck conversion, and energy storage components.
Title: Delay testing for power efficiency improvement (Mahroo Zandrahimi, TU Delft)
Voltage scaling techniques have been adopted widely for power optimization as well as process, voltage, and temperature variations compensation of integrated circuits. For cost and complexity reasons, these techniques are usually implemented by means of performance monitors allowing fast performance evaluation during production. In this work, we demonstrate the limitations of performance monitoring methodologies in terms of accuracy and effectiveness. By simulating ISCAS’99 benchmarks using the Nangate 45 nm open cell library, we show that the accuracy of these approaches is design dependent, and requires up to 15% added design margin, which can lead to unacceptable waste of power. Therefore, for more accurate delay estimation, more paths should be taken into account. One possible solution is using delay test patterns for delay estimation of a design to perform voltage scaling. Correlation between TF patterns and functional patterns has been proved Internally on a 28nm FD-SOI CPU. Moreover, Preliminary estimation gives a test time similar to the performance monitoring approaches.