BENEFIC project exhibition in ST, Grenoble, FR

On May 24, 2016, the BENEFIC project held an exhibition of the BENEFIC project in the showroom of STMicroelectronics in  Grenoble, France, to highlight the results of the project to a wider professional community and to the public. The event  brought together the various partners of the consortium where they presented a total of 9 demonstrators of the project. Lasting for 2 hours, the event generated strong interest from ST employees and visitors attracting about 100 attendees, who listened to talks about the BENEFIC project and engaged in interactive presentations of the demonstrators. In addition, local journalists where also present in the event, holding interviews with BENEFIC partners and disseminating the results of the project to science enthusiasts on web fora and other media outlets.

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Progress meeting of the BENEFIC EU project in ST Microelectronics, Paris, FR

On March 30, 2016, the partners of the BENEFIC EU project met together at the ST Microelectronics site in Paris, France to align their efforts in preparation for the final stage of the project. All aspects of the project were discussed ranging from technical to organizational and from basic technologies to applications. At the same time, there was a clear focus by the partners to integrate the various technologies developed within BENEFIC into the demonstrators of the project, to show the effectiveness of these new technologies and their practical impact in the industry.

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BENEFIC technology shortlisted in IET Innovation Awards 2015

The Far-Field Wireless Power Transfer (i.e., remotely powering devices, using radio waves) technology developed by IMEC as part of the BENEFIC project has been shortlisted for the IET Innovation Awards 2015. The technology uses a transmitter, consisting of an RF source and an antenna, that transmits a signal. The receiver in its most basic form consists of an antenna that is connected to a rectifier. This combination is known as rectenna. The receiving antenna intercepts part of the transmitted RF signal and this signal is converted to a DC signal using a diode or diode-based circuit.

Smart buildings of the future will be equipped with hundreds or maybe even thousands of wireless sensors. These sensors cannot be powered by cables or batteries due to the costs and environmental issues involved. This technology helps bring the dream of smart buildings closer to reality. More details about the awards can be found here.



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BENEFIC at European NanoElectronics Forum 2015

Various BENEFIC partners presented the BENEFIC project in the European Nanoelectronics Forum 2015, held in Berlin, Germany, on Dec 1-2, 2015. The BENEFIC booth boasted two demonstrators from NXP as well as IMEC. The NXP demo was an actual company demonstrator that illustrates the benefit of using ethernet communication for automotive applications to reduce the amount of copper wiring used in cars, along with a reduction to the energy needed to communicate between the various car components. This demo targets the “efficient energy distribution” objective of the project.
IMEC demonstrated their energy harvesting system, with an RF transmitter sending radio signals that can be captured by a small mobile antenna and transformed into electric power. The antenna powered a temperature sensor that was able to work totally autonomously, without the need for its own battery or power supply. This demo targets the “efficient energy generation” objective of the BENEFIC project. The demos received a lot of attention from the forum attendees and sparked much discussion about the possible applications and potential partnerships.

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BENEFIC technical session at CATRENE DTC 2015

On May 19, 2015, BENEFIC presented a technical session regarding Energy efficient MPSoC at CATRENE DTC in Dresden, Germany. The session was moderated by Armand Castillejo of STMicroelectronics. The following presentations were given by CEA Leti, IMEC, and TU Delft:

Title: Efficient Power Management in FD-SOI MPSoC (Diego Puschini, CEA)

UTBB FD-SOI technology offers new opportunities and challenges for circuit designers, promising extraordinary power saving and performance figures. This talk reviewed some basic concepts of dynamic power management and how the Dynamic Voltage-Frequency Scaling (DVFS) notion has evolved to Adaptive Voltage-Frequency Scaling (AVFS). With a special focus the constraints imposed by Multi-Processor System-on-Chip (MPSoC) architectures, AVFS is studied taking advantage of FD-SOI opportunities. This talk has presented some results obtained during the Catrene Benefic project: a power management technique that takes advantage of the very wide Body Biasing range offered by UTBB FD-SOI, in combination with efficient Adaptive Voltage and Frequency Scaling techniques. The proposed approach makes use of intelligent power mode selection in order to efficiently increase the total power saving. Results have been estimated on a 32-bit VLIW DSP with a Body Biasing Voltage scaling from 0V up to +/-1.5V combined with an AVFS mechanism in UTBB FD-SOI 28nm.

Title: A single-PCB miniature, efficient, 900MHz Rectenna for RF harvesting (Prof.dr. G. Dolmans, IMEC)

In the last decade, interest in wireless power transfer (WPT) has been reignited and since the latter half of this decade two distinct flavors of WPT have become apparent: short distance WPT by inductive charging and long distance WPT by RF transmission and reception. The main reason for renewed interest in longer distance, is believed due to the success of RFID and the recent advances in realizing low power electronics. With wireless sensors demanding average DC power in the range of tens of microwatts instead of tens of milliwatts, it has become feasible to power these sensors with long distance WPT. The recent advances of Holst Centre / Imec for a miniature 900 MHz long distance WPT system is shown, with improvements in sub-systems such as antenna, impedance matching circuits, rectifier circuits, boost-buck conversion, and energy storage components.

Title: Delay testing for power efficiency improvement (Mahroo Zandrahimi, TU Delft)

Voltage scaling techniques have been adopted widely for power optimization as well as process, voltage, and temperature variations compensation of integrated circuits. For cost and complexity reasons, these techniques are usually implemented by means of performance monitors allowing fast performance evaluation during production. In this work, we demonstrate the limitations of performance monitoring methodologies in terms of accuracy and effectiveness. By simulating ISCAS’99 benchmarks using the Nangate 45 nm open cell library, we show that the accuracy of these approaches is design dependent, and requires up to 15% added design margin, which can lead to unacceptable waste of power. Therefore, for more accurate delay estimation, more paths should be taken into account. One possible solution is using delay test patterns for delay estimation of a design to perform voltage scaling. Correlation between TF patterns and functional patterns has been proved Internally on a 28nm FD-SOI CPU. Moreover, Preliminary estimation gives a test time similar to the performance monitoring approaches.
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BENEFIC second review on March 18,2015

The 2nd official BENEFIC technical review has been performed on March 18,2014 by the Catrene review officials.The Catrene representative heading the review were Peter Koch, Reiner Kohl, Herbert Roedig, Sheherezade Azizi and the public authority representative for France Eric Mottin.

The review took place at the STMicroelectronics site in Paris,France with attendance and support of representatives of all partners. The review was led by the project coordinator Armand Castillejo of STMicroelectronics.

The review took about 4 hours, with presentations of the project and work package leaders. The reviewers complimented the partners with the good presentations and the clear evidence that the project is very alive and running with the partners showing eagerness for structure and co-operation. The BENEFIC partners received clear feedback and recommendations for further structuring of the project, targets and exploitation.


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BENEFIC 2nd power seminar

On March 17, 2015, the 2nd BENEFIC power seminar was held at the Paris site of ST-Microelectronics with the attendance of project partners. Various presentations were given to discuss the current status of research and development around new Power Efficiency techniques. Mains presentations were given by major clusters of partners inside the consortium :

  • Smart Test Patterns for Power Efficiency Improvement
  • Power Efficient Low Power RF Front end Components
  • Energy Efficiency for Heterogeneous Multicore Architectures
  • Efficient Power Management in FD-SOI MPSoC

A number of recent advances were shown and plans for future work were discussed. As a result, partners gained a better understanding of the work being performed in the project and possible further collaboration opportunities between partners were identified.


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BENEFIC at European NanoElectronics Forum 2014







The BENEFIC consortium attended the European NanoElectronics Forum 2014 on 26-27 November, 2014 in Cannes, France. During the forum, the BENEFIC partners have presented the project current results, in order to inform the nanoelectronics community and develop further collaborations with interested industrial parties.

BENEFIC participated in the project village session with a poster and two demos presented by Thales Communications & Security (TCS) and LEAT University of Nice Sophia Antipolis. It was a great opportunity to meet with different people in the community and get feedback on the demos and the project.

The first demo is the first stage of the TCS demonstrator. The objective is to demonstrate the enhancement of energy efficiency and energy saving toward Energy Neutral Operational (ENO) platforms on behalf of Hardware Dependent Software (HdS) based tool, a software code generator optimizing hardware resources to achieve a specific quality of service. At this stage of the demonstrator, an STM32 board from STM is already embedded, and a power reduction by a factor 2 to 10 is expected.

The second demo is a work on power consumption exploration and analysis. LEAT have shown the definition of a low power scheduling strategy for heterogeneous dynamically reconfigurable multicore/manycore architectures and had positive and encouraging reactions. The current results already show 1.5x energy savings with 2x performance benefits on a test benchmark application.


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Recore Systems announces FlexaWare

During electronica 2014 in Munich next week, Recore Systems announces FlexaWare®, an easy programmable, flexible many-core embedded platform. The FlexaWare® platform consists of hardware, a runtime and a software development environment. It is designed from the ground up to offer the flexibility and scalability needed to cater to a range of applications from clear cut to compute intensive and massively parallel.

Many developers view heterogeneous many-core systems as the programmer’s nightmare. Recore Systems developed the FlexaWare scalable embedded parallel data processing platform to offer the much needed ease of use and flexibility. FlexaWare’s programming model and hardware architecture enable a many-core platform that is easy to program and that at the same time scales flexibly to specific application demands.

FlexaWare’s software development environment (SDE) gives the programmer a high-level, uniform view of the hardware while the hardware under the hood is a heterogeneous mixture of general purpose cores, signal processing cores, and hardware accelerators suited to offer the best match for a specific application domain. To translate the abstraction in FlexaWare’s SDE to efficient performance on the many-core hardware, Recore Systems introduces a lightweight distributed coordination layer, the so-called FlexaWare runtime.

“For easy programming of a heterogeneous many-core processor system, the programming model is key,” says Gerard Rauwerda, CTO at Recore Systems. “FlexaWare runtime keeps track of what is happening on the system, and knows how the hardware can deliver if a task needs to run real-time and with high performance, or in contrast using low power. The intelligence in the FlexaWare runtime sets FlexaWare apart from standard embedded platforms and makes the heterogeneous many-core easy to program. This is crucial to support applications running on a large number of cores.”

For more information on FlexaWare, see


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SpyGlass Physical 3D training

Atrenta France is planning to make a training on Early Design Planning using SpyGlass Physical 3D.
The purpose of the training is to help reduce iterations for back-end engineers by preparing earlier their partitioning strategy and die floorplanning. The training will take place in Grenoble, for about half a day, hands-on exercise included. We will fix the date depending on the participants availabilities.

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