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On Jun 27, 2024, the HW Acceleration Network community and SURF organize a HW acceleration workshop focused on tools and HW platforms for accelerating AI workloads. This workshop is part of the “FIRE: FPGA Innovation Research Exchange“ series of events.

You are invited to join us! Please register using this link.

The event features a lineup of discussions centered around cutting-edge computing technologies for AI workload acceleration showcasing multiple industrial players such as Innatera and Groq as well as developers of HW acceleration platforms such as AMD and Altera. In addition, the workshop features two keynote talks on future computing platforms dedicated to quantum computing as well as cellular automata.

Where: SURF Utrecht (Moreelsepark 48, 3511 EP, Utrecht)
When: June 27, 2024, 9.30-17.00

The outline of the program of the event is as follows.

09.30 – 09.45: Welcome&Coffee
09.45 – 10.00: Introduction and updates
10.00 – 11.00: Keynote 1
11.00 – 12.30: Platforms for AI acceleration session
12.30 – 13.30: Lunch
13.30 – 14.30: Keynote 2
14.30 – 15.00: Flash talks
15.00 – 15.30: Coffee break
15.30 – 17.00: Tools for accelerator platforms session
17.00 – 17.30: Drinks

On Dec 6-2023, SURF organizes, together with the HW Acceleration Network community, a HW acceleration workshop focused on application development using a HW-SW co-design approach. This workshop is part of the “FIRE: FPGA Innovation Research Exchange“ series of events.

You are invited! Please register using this link.

The focus of this event is on optimizing applications on heterogeneous CPU-accelerator systems, addressing system design challenges to achieve full system optimization. We invite speakers from industry and academia to share their thoughts and experiences in using GPU and FPGA accelerated systems for a number of relevant applications domains.

Where: SURF Utrecht (Moreelsepark 48, 3511 EP, Utrecht)
When: December 6, 2023, 9.45-17.00

The outline of the program of the event is as follows.

09:45 – 10:15: Welcome&Coffee
10:15 – 10:30: Introduction and updates
10:30 – 12:00: HWACC acceleration session
12:00 – 13:00: Lunch
13:00 – 14:30: Keynotes session
14:30 – 15:00: Coffee break
15:00 – 17:00: FIRE talks session

On June 21-22, SURF organizes, together with the HW Acceleration Network community, an FPGA for HPC seminar, under the name “FIRE: FPGA Innovation Research Exchange“.

You are invited!

This is the first of a series of workshops which brings together FPGA practitioners, Computer Science and Engineering experts, Scientific Computing experts and application owners, and HPC providers, in an effort to build a community to evaluate the need and usability of FPGAs in HPC and Scientific Computing. The event takes place in Utrecht, at Moreelsepark 48, from June 21 to June 22, 9:00 to 17:30.

We planned an exciting program!

On the first day, we have 3 plenary talks by researchers in the HWAccel community (June 21, morning), two invited talks from an FPGAs integrator (University of Paderborn) and an FPGA vendor (Xilinx) (June 21, after-lunch), and a set of selected pitches from the community, those using (or wanting to use) FPGAs for their own computational science applications and tools (June 21, afternoon). These pitches are selected to stir discussion and assess the potential impact of FPGAs for different domains, specialists, experts, and SURF.
Day two (June 22) is reserved for an FPGA programming tutorial by Xilinx.

We have a limited number of seats. Please contact us if you are interested to join.

This event offers several in-depth presentations around data movement and data access for accelerators. This will be the first live event where we can meet each other in person. We have scheduled several time slots i n the event (lunch, posters, break, round table and drinks) to meet other engineers and researchers working with hardware acceleration and to exchange ideas. 

The event will be hosted in SURF Utrecht at the Moreelsepark 48, on Nov 4, 2022, 12:00 – 17:00. Please register for the event using the following link. You may forward this registration link to your colleagues in the field.

https://events.surf.nl/Kort12altered/open/eaadda78-677f-4ec8-9842-5690bdba3e73?culture=en-US

We ask every participant, on voluntary basis, to bring a poster (A3 or A4 format) to present the topics that you are working on to the other participants. The posters will be on display during lunch, coffee break and drinks to spark interest and start conversations.

Event program
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12:00 – 13:15 Arrival with coffee + lunch, posters
13:15 – 13:30 Introduction Hardware Acceleration Network (Zaid Al-Ars, TUDelft)
13:30 – 14:00 High Performance Python analytics using hardware acceleration (Joost Hoozemans, Voltron Data)
14:00 – 14:30 Optimizing data movement for GPU/FPGA accelerator cards: a bioinformatics case study (Nikolaos Alachiotis, UTwente)

14:30 – 15:00 break, coffee/tea, posters

15:00 – 15:30 Data transport in a radio telescope: Remote Direct Memory Access over Ethernet from FPGA to GPU (Steven van der Vlugt, ASTRON)
15:30 – 15:45 Innovating with SURF (Raymond Oonk, SURF)
15:45-16:00 Processing 4 TB/s of HEP data on GPUs (Roel Aaij, NIKHEF, and Daniel Campora, Maastricht University)
16:00 – 16:30 Round table (Zaid Al-Ars, TUDelft)

16:30 – 17:00 Drinks, posters

We would like to invite you to a new online event organized by our HW Acceleration Network NL. Based on your feedback in the previous event, the focus of this event will be on “Tools for HW acceleration”, with topics ranging from OpenCL and Vitis to machine learning model synthesis.

The event will be held on Jan 15, 2021, 15:00 – 17:00. Please register through the form in the LinkedIn post or by email (info@hwacc.nl).

Below, you’ll find the program of the event. Details of the talks that will take place can be found in the form. Looking forward to meeting you again virtually.

Program:
14:45 – 15:00 Zoom link open. Walk-in welcome

15:00 – 15:10 Welcome, introductions and update on network
15:10 – 15:30 Steven van der Vlugt, ASTRON. High Level FPGA Programming in the Industry
15:30 – 15:50 Stefano Corda, TU/e. Radio-astronomical imaging acceleration on Xilinx Vitis

15:50 – 16:00 Break, grab your drink and chit-chat

16:00 – 16:20 Jan Kuper, QbayLogic. Model Based FPGA Design using Clash
16:20 – 16:40 Jakoba Petri-Koenig, TUDelft/Xilinx. FINN: Fast, Scalable Neural Network Inference on FPGAs
16:40 – 17:00 Discussion, Q&A and feedback.

On September 18, 2020, we organized the very first event in our Hardware Acceleration Network NL, with speakers from both industry and academia, such as ASML, Synopsys and ASTRON, and lots of community interest. Various topics were discussed representing challenges and opportunities in the field of computing hardware acceleration. The event attracted about 30 participants and was organized online. The program of the event was as follows.

Event Timing: Sep 18, 2020, 15:00 – 17:00
Event Address: Online, login instructions will follow
Contact us at steven.vandervlugt@gmail.com or z.al-ars@tudelft.nl

Program
14:45 – 15:00 Zoom link open. Walk-in welcome

15:00 – 15:15 Introduction. Ambition and goals of HW Acceleration Network NL
15:15 – 15:30 John Romein, ASTRON: Technological Innovations in the Processing of Radio-Astronomical Data
15:30 – 15:45 Roel Jordans, TU Eindhoven: Efficient and reliable hardware acceleration, the art of combining opposites
15:45 – 16:00 Mohamed Bamakhrama, Synopsys: Energy-Efficient Deep Neural Networks

16:00 – 16:15 Break, grab your drink and chit-chat 

16:15 – 16:30 Andre Kokkeler, U Twente: High-performance computing at the University of Twente
16:30 – 16:45 Lennart Noordsij, ASML: Fast parallel decompression to overcome the PCIe bottleneck
16:45 – 17:00 Joost Hoozemans, TU Delft: Enabling HW Acceleration for the Big Data Ecosystem
17:00 – 17:15 Round table about common goals and future plans

17:15 – 17:30 Grab your drink and chit-chat  

A news article about the event was published on the ASTRON website.