Event on Accelerated Applications Using HW-SW Co-design
Date: December 6, 2023

On December 6, 2023, we held our second event in the “FIRE: FPGA Innovation Research Exchange“ series of events. This event was organized together with SURF, and consisted of a HW acceleration workshop focused on application development using HW-SW co-design approaches. The event addressed the challenge of optimizing applications on heterogeneous CPU-accelerator systems to achieve full system optimization. We had a number of keynote speakers from industry, academia and research institutes. In addition, we organized a session with 5-minute flash presentations, where many researchers and companies presented their innovations and products at a high pace to engender collaboration and information exchange. The event was a full-day event and was fully booked, attended by about 70 participants.

FIRE: FPGA Innovation Research Exchange
Date: June 21, 2023

On June 21-22, 2023, SURF in Utrecht hosted the inaugural FIRE event. The first day featured informative talks from the hardware acceleration community, including keynote speeches from Christian Plessl of the Paderborn Center for Parallel Computing and Lucian Petrica from AMD Xilinx. Christian provided insights on Heterogeneous Accelerated Computing, covering architectural design, software, and application perspectives. Researchers also presented their successful use of this technology and its potential benefits across various fields throughout the event. You can find the slides of all the presentations at the symposium via this link.

The second day featured a tutorial on using FPGA tools to design, implement, analyze and debug hardware architectures. Various participants were able to have first-hand experience with hardware design workflows and successfully implement their accelerated applications.

This event is part of the FIRE series, held in collaboration with SURF, as we promote the future of computing and networking program that strives to identify the impact of different technologies for applications in research. To achieve this, we collaborate with various academic and industrial partners to organize these series of workshops. These events bring together researchers from various fields, such as high-performance computing, computational science, data science, electrical and performance engineering, to explore the role and significance of FPGA technology in the future of Dutch advanced computing. We aim to share tools, applications, and best practices to create a community that advances the research and use of FPGA technology in the Netherlands.

Data Movement Acceleration Event
Date: November 4, 2022

On Friday, November 4, 2022, we held a new HW Acceleration Network event focusing on the topic of Data Movement Acceleration. This is the first post-corona in-person event held in Utrecht at the offices of the SURF Cooperative. We received more that 60 participants, reaching full capacity, attracting representatives of academia as well as small and large industrial partners in the Netherlands.

The speakers gave several in-depth presentations around data movement and data access for accelerators. The talks addressed a number of topics ranging from transparent data movement for high-level language acceleration, to data communication between FPGAs and GPUs on heterogeneous compute systems. Joost Hoozemans from Voltron Data started with a talk on “High performance Python analytics using hardware acceleration”, followed by Nikolaos Alachiotis from UTwente with a talk on “Optimizing data movement for GPU/FPGA accelerator cards: a bioinformatics case study”. Then Steven van der Vlugt from ASTRON presented on “Data transport in a radio telescope: remote direct memory access over Ethernet from FPGA to GPU”, after which Roel Aaij from NIKHEF talked about “Processing 4 TB/s of HEP data on GPUs”. We also had a talk from our hosts at SURF given by Raymond Oonk on the innovations and collaborations SURF provides.

In addition, several breaks were organized to discuss the various technology posters of participants in addition to discussion of collaboration opportunities. The closing roundtable discussion was engaging and provided valuable feedback on the event and possible future topics of interest to the participants.


Event on enabling high-performance applications in the industry
Date: October 29, 2021

As industrial practices are increasingly integrating accelerated solutions into their compute workflows, various challenges are being identified and addressed to ensure effective deployments of such solutions in practice. This event focused on the opportunities and practices of industrial partners develop to enable the current trend of heterogeneous computing. This on-line event was attended by more than 40 participants interested in learning from current best practices and exchanging ideas.

The event started with a talk by Peter Hofstee (IBM) on “Breaking the memory bottleneck in high-performance computing”, where new memory interconnect technologies were discussed that makes acceleration more effective. This was followed by Rob de Jong (Philips) with a talk on integrating HW accelerated into medical devices, titled “High-performance image processing for medical applications: challenges and solutions”. Then, Dirk van den Heuvel (Topic Embedded Systems) gave talk titled “Exascale high-performance computing: Infrastructural and modeling concept” on deployment of large scale accelerated systems for scientific computing. Finally, Joost Hoozemans (Teratide) discussed efficient ways to use heterogenous computing in the field in his talk titled “Efficient data-centric computing using heterogeneous accelerator system”.

Tools for HW Acceleration Event
Date: January 15, 2021

Based on the feedback we received from the attendees in the first HW Acceleration event, many partners were interested in learning more about the available tools for automating the HW design processes for dedicated algorithms. Therefore, we organized an on-line event on January 15, 2021, to discuss available design automation tools for FPGAs. The event attracted a lot of interest with more than 30 partners joining remotely to listen in to the talks.

The topics discussed in the event range from OpenCL and Vitis high-level synthesis tools to machine learning model synthesis. The first talk was given by Steven van der Vlugt (ASTRON) on the topic of “High Level FPGA Programming in the Industry”, discussing use cases of using high-level synthesis tools in high-tech companies such as ASML and Philips. This was followed with a talk by Stefano Corda (TU/e) on using the Vitis framework titled “Radio-astronomical imaging acceleration on Xilinx Vitis”. Then, Jan Kuper (QbayLogic) gave a talk on “Model Based FPGA Design using Clash”, addressing a specialized toolchain to automate dataflow HW designs. Finally, Jakoba Petri-Koenig (TUDelft/Xilinx) gave a talk about “FINN: Fast, Scalable Neural Network Inference on FPGAs” which is a leading framework for automatic synthesis of ML models on HW.

The event ended with an open discussion where partners exchanged ideas about the current challenges and future solutions for HW design on FPGAs.

The First Hardware Acceleration Network meetup
Date: September 18, 2020

Submitter: Steven van der Vlugt
Description: On Friday, September 18, 2020, we held our first HW Acceleration Network meetup with 28 participants!

The idea for a Dutch network for hardware acceleration(*) originates from a dinner at the Xilinx Developer Forum in November 2019 in The Hague, NL, where we observed that the Xilinx event topics had moved in about 5 years’ time from roughly a balance of 95% firmware and 5% software to about 10% firmware and 90% software. During the event we met with a group of colleagues of a former EU project where we also worked on this topic and concluded that many people in the Netherlands are working with this kind of technology, but it was hard to reach out to others.

After this initial idea, we reached out to our network and set-up a core team with Zaid Al-Ars (TUDelft), Roel Jordans (TU Eindhoven), André Kokkeler (U Twente) and Steven van der Vlugt (ASTRON). We were granted funding from the 4TU.NIRICT community funding program to organize our events. A first event to form a network or community in this area was scheduled for March 2020, but had to be postponed due to COVID-19. Given circumstances we had to start with an online event.

During the event we presented our view on Hardware Acceleration and invited others to share their work in this area. Special thanks to Roel Jordans (TU/e), John Romein (ASTRON), Mohamed Bamakhrama (Synopsys), Daniel Ziener and Nikolaos Alachiotis (U Twente), Lennart Noordsij (ASML) and Joost Hoozemans (TUDelft) for presenting their work!

Despite online not being the ideal form to organize this event we consider it a success! It was good to see familiar faces and connect with new people in the same industry and we already had nice interaction on several topics, also our view of Hardware Acceleration resonated well.

During the coming period we will define how to proceed with the network and in what form to organize a next meetup. In the meantime, we use a LinkedIn group to ask questions to each other, exchange thoughts on novel topics or meet new people working on the same challenges. Feel free to join the group if you are interested in this area or contact us for questions.

(*) We define hardware acceleration as: the optimization of software to specific hardware architectures utilizing the hardware specific characteristics to improve performance or optimize the system.